The present invention relates to a vector logical operation apparatus for vector data and a vector processor using such a vector logical operation apparatus.
In a prior art vector processor, there is provided an instruction to speed up processing of A(J)=A(J-1)*B(J)+C(J) in a FORTRAN sentence as means for reflecting a result of operation performed by using a J-th element data of the vector data to an operation performed by using (J+1)th and following element data, where * and+ represent arithmetic product and arithmetic sum and A(J) represents the J-th element in an array data A. One example is disclosed in U.S. Pat. No. 4,525,796 issued on June 25, 1985. In image processing and logical simulation, the arithmetic product and the arithmetic sum in the above formula are substituted by logical product and logical sum, but they cannot be vector-processed.